Josh Huang黃致學
PRINCIPAL DIGITAL IC DESIGNER|AI-NATIVE RTL WORKFLOW PIONEER
General Description
CS-educated (NCTU / NTHU) digital IC designer with 18+ years of high-performance silicon design across MStar, Ubiquiti, Bitmain/Cvitek and ASPEED. Specializes in “software-defined hardware design” — using a computer-science background to re-architect traditional EDA environments rather than operate inside their defaults.
Currently a high-intensity ChipAgents power user, having built a proprietary methodology for the “last mile” of AI in RTL design: agentic close-loop systems for autonomous testing, real-time error correction, and full-stack architecture standardization.
Earlier chapters span ISP system architecture for silicon that shipped as BM1880V2 / CV1835 / CV1820, RTL for Ubiquiti’s airFiber LTU and GPON OLT product lines, and 34+ taped-out chips at MStar across 2G basebands, video codecs and touch/display IP.
Features
Digital IC Design & Leadership
High-speed RTL (Verilog/SystemVerilog), ISP 3A/HDR/CFC, BMC architecture, timing closure, power/area optimization, CDC, formal verification, automated ECO, CPF low-power flow.
Agentic Mastery
“Divide-and-conquer” agent guiding, real-time agent pivoting, context/memory management for complex RTL generation via ChipAgents.
Automation & Infrastructure
Python (FastAPI/CLI), C/C++ (DPI-C), Perl, Tcl/Tk, Jenkins CI/CD (22+ jobs), Docker, QEMU, SVN/Git/P4.
EDA Flow Innovation
Full-stack unified design environments (C-model to firmware), bit-true co-simulation, Cadence Conformal LEC, VMM/UVM verification IP, automated regression.
Applications — Experience
— PRESENTcurrent
- Directed ChipAgents through 20+ iterative modifications to architect a production-grade ISP Auto Focus module — 100% coding-style compliance and timing closure inside an autonomous, close-loop environment.
- Architected a full-stack unified IP flow (C-model → firmware) across 103 IP modules: design, synthesis, lint, LEC, ECO and firmware-header generation with zero-manual-intervention handoffs across the HW/SW boundary.
- Built an autonomous ISP bit-true co-simulation framework (DPI-C) for 6+ core ISP modules, debugging EOF/EOL pipeline-sync issues to 100% bit-true alignment.
- Re-engineered SmartSramGen from a simple Q&A model into a ChipAgents-driven autonomous system self-correcting across 600+ instances.
- Developed a “strategic guiding” methodology that overcame agentic-adoption friction for senior engineers reverting to legacy flows — internal champion for AI-native workflows.
- Optimized 22 Jenkins pipeline jobs and used AI for knowledge management, cutting RTL team onboarding time.
— JUN 2022
- Major contributor to ISP designs across Bitmain / ICLink / Wisecore / Cvitek — AE, HIST, AF, AWB, GMS, LSCM, DCI, LDCI, FPN, BLC, WBG.
- IP shipped in every chip taped out on the line: BM1880V2, CV1835, CV1820 — top subsystem integration, IP and system verification.
- Built and maintained the ISP IP verification environment; developed the ISP system addressing automation flow.
- Owned the Jenkins-CI regression flow; built ISP C-model co-simulation and integration with RTL.
- Architected IP block structure and translation from C-model; drove IP cost-down and power-saving.
— JUN 2018
- Designed RTL blocks for shipping communications products — airFiber LTU (FFT/iFFT engines, batch programmer engine, DFS engine, memory wrappers) and GPON OLT, in Verilog/SystemVerilog.
- Integrated million-gate 28nm ASICs through synthesis, CDC, formal verification, automated ECO, and power & timing closure.
- Brought up airFiber LTE in the field and debugged post-silicon CPU/bus issues.
- Ran block- and chip-level verification on FPGA (Altera and Xilinx); developed the automated ECO flow for Conformal ECO.
- Introduced elegant SystemVerilog methods — interfaces, parameterization, assertions — and a Jenkins-CI regression system.
- Developed ARM-DSM simulations, a NAND controller, an LVDS companion-RF interface, and a U-Boot driver for Altera’s low-latency 10GbE MAC/PHY.
- Worked daily across sites in America, Europe and Asia.
— DEC 2013
- Owned RTL design SPEC-to-tapeout for touch screen, 2G digital baseband, video codec (AVC/H.264, RMVB, VP6, HEVC/H.265), AMBA/bus-protocol translation, memory BIST/scan-ATPG (DFT), power-aware gating and SIM-card IP.
- Built VMM/UVM SystemVerilog verification environments and a reusable OCP verification IP.
- Ran ARM/DSP-based design and simulation with C-code co-simulation.
- Generated RTL via Perl/TCL; built “dropzone,” an automated regression system in Python/Perl/crontab.
- Participated in 34+ taped-out chips — A/D TV, 2G/3G handset, set-top box and GPS — from .18µm down to 28nm.
- Equipment-level debug with oscilloscope, JTAG ICE, logic analyzer and Keithley source meters.
Education
– 2007
– 2005
Notes — Honors & Certificates
| 2013.07 | TOEIC — scored 905/990. “Ability to communicate effectively in almost any situation.” |
| 2012 | MStar Semiconductor Short-Term Reward Winner |
| 2011 | MStar Semiconductor Short-Term Reward Winner |
| 2013 | Google Code Jam — Qualification Round passed |
| 2006.05 | GEPT (General English Proficiency Test) — High-Intermediate level |
| 2005 | Trend Micro Programming Contest — network monitoring system, C/C++ |